KAIST Unveils Revolutionary 'Nano Sandpaper' for Atomic-Level Semiconductor Processing

KAIST researchers have developed a groundbreaking 'nano sandpaper' utilizing carbon nanotubes, poised to transform semiconductor surface processing by achieving uniform precision at the atomic level. This innovative technology holds immense potential for enhancing surface quality and processing accuracy in advanced semiconductor manufacturing, including crucial components like high-bandwidth memory (HBM).

Overcoming Current Polishing Hurdles

Traditional methods for surface smoothing, such as conventional sandpaper, fall short of the extreme precision demanded by modern semiconductors due to difficulties in uniformly securing ultrafine abrasive particles. The industry standard, Chemical Mechanical Polishing (CMP), relies on chemical slurries. While effective, CMP necessitates additional cleaning steps and generates substantial waste, making it a complex and environmentally burdensome process.

Current methods like CMP are complex, environmentally burdensome, and lack the atomic-level precision required for advanced semiconductors.

The Innovation: Carbon Nanotube Nano Sandpaper

To address these challenges, a research team led by Professor Sanha Kim from KAIST's Department of Mechanical Engineering engineered the novel nano sandpaper. This breakthrough involves vertically aligning carbon nanotubes—tens of thousands of times thinner than a human hair—within a durable polyurethane matrix, with their tips partially exposed on the surface. This unique structural design effectively prevents abrasive detachment, ensuring stable and consistent performance across repeated uses without concerns of surface damage.

Unprecedented Precision and Performance

The developed nano sandpaper boasts an astonishing abrasive density. It exceeds 1,000,000,000 grit, which is approximately 500,000 times higher than the finest commercially available sandpaper. This incredibly dense arrangement enables surface processing precision down to several nanometers, equivalent to the thickness of just a few atoms.

Experimental trials unequivocally confirmed the nano sandpaper's effectiveness. It successfully polished rough copper surfaces to nanometer-level smoothness. Furthermore, in semiconductor pattern planarization experiments, the technology remarkably reduced dishing defects by up to 67% compared to conventional CMP processes. Dishing defects, where interconnect lines become recessed, are a critical issue impacting the performance and reliability of advanced semiconductors like HBM.

A Greener Future for Semiconductor Manufacturing

A significant environmental advantage of this technology is its departure from the conventional need for a continuous supply of slurry solutions. Because the abrasive materials are permanently fixed on the sandpaper surface, the new process drastically reduces the need for subsequent cleaning steps and completely eliminates waste slurry. This paves the way for a more environmentally friendly and sustainable approach to semiconductor manufacturing.

The nano sandpaper eliminates the need for slurry, reducing waste and paving the way for more environmentally friendly semiconductor manufacturing.

Broadening Applications and Future Impact

Researchers anticipate that this transformative technology will find broad application in advanced semiconductor planarization processes, particularly for HBM used in AI servers, and for hybrid bonding processes—an emerging next-generation semiconductor interconnection technology. The study underscores a remarkable expansion of the everyday concept of sandpaper into the realm of nano-precision processing.

The research, with Dr. Sukkyung Kang of the Department of Mechanical Engineering as the first author, received the Gold Prize in the Mechanical Engineering Division at the 31st Samsung Human Tech Paper Award. It was published online on January 8, 2026, in the international journal Advanced Composites and Hybrid Materials.