Silicon 'High-Rises': A New Path Beyond Moore's Law

Researchers at the University of Illinois Grainger College of Engineering, led by Professor Qing Cao, have developed a method for stacking multiple layers of silicon electronics vertically. The process uses ultrathin silicon nanomembranes transferred at temperatures below 200°C, staying within the thermal budget limit of 400°C required for monolithic 3D integration.

"With vertical integration, you can distribute them across multiple layers. It's like replacing a sprawling suburb with high-rises." — Professor Qing Cao

The Breakthrough

The team fabricated three stacked layers, each containing 625 transistors, achieving device yields of 98–100%. The transistors are junctionless, uniformly doped before stacking to avoid high-temperature doping steps.

Output current densities match those of conventional silicon transistors fabricated at higher temperatures, and outperform monolithic devices made from alternative materials by a factor of three to four.

The layers were connected using vertical metal interconnects, and 3D logic circuits and static random-access memory cells were successfully demonstrated. The findings were published in Nature.

The Context: Moore's Law and Its Limits

Moore's law, predicting transistor density doubling every two years, faces physical limits as transistors approach atomic scales and quantum effects.

Current commercial 3D chips stack separately manufactured wafers (e.g., high-bandwidth memory, AMD's 3D V-Cache), but have coarse alignment and large vertical connections.

Monolithic 3D integration fabricates each new device layer directly on top of the previous one, allowing denser vertical connections and nanometer-scale alignment. Previous attempts used alternative materials due to temperature constraints, but those materials suffered performance and reliability issues.

Why This Matters

"For the first time, we have met the thermal budget of monolithic 3D integration using standard single-crystalline silicon and delivered unprecedented performance." — Professor Qing Cao

The researchers are preparing to transfer the technology to an industrial semiconductor foundry. Cao added: "You can keep stacking layers beyond the three we demonstrated. We now have a strong foundation for transferring this technology."

The work is supported by the Center for Advanced Semiconductor Chips with Accelerated Performance, whose industry partners include IBM, Intel, and TSMC.